1. Field of the Invention
This invention relates to a programmable semiconductor memory using non-volatile transistors as memory cells from which data can be electrically erased. It particularly relates to a non-volatile semiconductor memory in which data stored in a plurality of memory cells may be erased simultaneously, in units of a block, or in units of a column. Data may be written to the memory a cell (or bit) at a time.
2. Description of the Prior Art
A non-volatile transistor memory which permits erasure of data is known as an EPROM (Erasable and Programmable Read Only Memory). An EPROM from which data may be erased electrically is called an E.sup.2 PROM (Electrically Erasable PROM). E.sup.2 PROMs have been developed which permit the simultaneous erasure of data stored in a plurality of memory cells. Such an E.sup.2 PROM is disclosed in "A 128K Flash EEPROM Using Double Polysilicon Technology", pp. 76-77 of "1987 IEEE International Solid State Circuits Conference, Digest of Technical Papers."
FIG. 11 is a circuit diagram depicting a conventional E.sup.2 PROM memory cell array using the cells described in the above-mentioned document. In this Figure, memory cells 90 consist of non-volatile transistors having a floating gate electrode and a control gate electrode. Data erasure may be effected electrically. Memory cells 90 are arranged in a row and column matrix. The drains of each memory cell 90 in a given row of memory cells (which are horizontal as seen in the drawing) are respectively coupled to the same one of bit lines 91. The sources of the memory cells 90 in a given row of memory cells are respectively coupled to the same one of ground lines 92. The control gate electrodes of the memory cells 90 in a given column of memory cells (which are vertical as seen in the drawing) are respectively coupled to the same one of column lines 93. In this memory, data may be read or written by the selective imposition of set voltages on a given bit line 91 and column line 93 to select a particular 1-bit cell. Block data erasure of all the bits can be effected by the simultaneous imposition of a set voltage on all the bit lines 91.
This memory permits large-scale integration of cells since each cell or bit consists of a single non-volatile transistor. However, data erasure may only be effected in the cells simultaneously or in units of a row. It is not possible to effect data erasure in units of a byte, the processing unit for parallel read/write memories.
The prior art does disclose an E.sup.2 PROM which permits data erasure in byte units. Reference is made, for example to "A Million-cycle CMOS 256K EEPROM", pp. 78-79 of "1987 IEEE International Solid-State Circuits Conference, Digest of Technical Papers." However, large-scale integration of cells is not possible with the memory disclosed therein, since each 1-bit memory cell comprises two or four transistors.